Verification Environment for a SCMP Architecture

Author

Yao, Wenbin ; Yao, Nianmin ; Cai, Shaobin ; Ni, Jun

Author_Institution

Coll. of Comput. Sci. & Technol., Harbin Eng. Univ.

Volume

2

fYear

2006

fDate

20-24 June 2006

Firstpage

787

Lastpage

791

Abstract

The computer architecture of single-chip multiprocessor (SCMP) is one of important research topics in developing the next-generation of computer hardware. A verification environment in the SCMP architecture, base of RISC microprocessor, acts as a functional verification simulator that elaborates its functions. This paper reports a simulation of the operational behavior in terms of function units. The simulation was in the mode of cycle-by-cycle when programs execute. The results of the SCMP simulation show that the simulation and its implementation can be used to effectively study the feasibility and applicability of the SCMP architecture

Keywords

formal verification; logic simulation; microprocessor chips; multiprocessing systems; reduced instruction set computing; RISC microprocessor; SCMP architecture; computer architecture; functional verification simulator; single-chip multiprocessor; verification environment; Analytical models; Computational modeling; Computer architecture; Computer science; Educational institutions; Flowcharts; Hardware; Logic; Microprocessors; Reduced instruction set computing;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer and Computational Sciences, 2006. IMSCCS '06. First International Multi-Symposiums on

Conference_Location

Hanzhou, Zhejiang

Print_ISBN

0-7695-2581-4

Type

conf

DOI

10.1109/IMSCCS.2006.283

Filename

4673804