Scan chain and power delivery network synthesis for pre-bond test of 3D ICs

Author

Panth, Shreepad ; Lim, Sung Kyu

Author_Institution

Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

fYear

2011

fDate

1-5 May 2011

Firstpage

26

Lastpage

31

Abstract

Pre-bond testing of 3D ICs improves yield by preventing bad dies and/or wafers from being used in the final 3D stack. However, pre-bond testing is challenging because it requires special scan chains and power delivery mechanism. Any 3D scan chains that traverse multiple dies will be fragmentized in each individual die during pre-bond testing. In this paper we study the scan chain and power delivery network synthesis for pre-bond testing of 3D ICs. The testing of individual dies is facilitated by the addition of dedicated probe pads for power delivery and scan IO as a form of design-for-testing. We investigate the impact of scan-chain Through-Silicon-Vias (TSVs) on power consumption and voltage drop. We also study the requirements of power probe pads for power delivery during pre-bond structural test.

Keywords

electric potential; integrated circuit testing; three-dimensional integrated circuits; 3D IC; TSV; design-for-testing; final 3D stack; power consumption; power delivery network synthesis; prebond structural test; scan IO; scan-chain through-silicon-vias; voltage drop; wafers; Probes; Resistance; Testing; Three dimensional displays; Through-silicon vias; Wires; 3D ICs; power delivery network; pre-bond test; probe test; structural test;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium (VTS), 2011 IEEE 29th

Conference_Location

Dana Point, CA

ISSN

1093-0167

Print_ISBN

978-1-61284-657-6

Type

conf

DOI

10.1109/VTS.2011.5783750

Filename

5783750