Macromodeling of digital libraries for substrate noise analysis

The demand for low cost, low power, and small area electronic device calls for system-on-a-chip (SoC) designs. Integration of complex digital blocks and high performance analog functions onto single SoCs induces signal integrity between noisy digital circuits and sensitive analog sections. Such signal integrity degrades the performance of analog circuits and even causes functional failures of victim circuits. In order to account for this interference in circuit design phases, substrate noise analysis becomes particularly important, especially in deep submicron digital and mixed-signal circuits. To this end, it is critical to estimate efficiently and accurately the noise injection from the digital circuits with tens of millions of transistors. In this work, we develop techniques that automatically extract low-complexity time-varying macromodels for digital blocks, at the cell library building phase. Tailored for substrate noise analysis, the extracted macromodel includes three major noise injection mechanisms. The efficacy and accuracy of our macromodel are confirmed in the simulation results. Thanks to the linear time-varying (LTV) model reduction based on the time-varying Pade (TVP) method, our macromodel extraction features high accuracy with affordable complexity. Equally attractive is the accurate-by-construction substrate noise model generation by merging the macromodel extraction into cell library building phase.