DocumentCode
3377722
Title
Energy-efficient time-interleaved and pipelined SAR ADCs
Author
Lin, Jiaming ; Yu, Wenhuan ; Temes, Gabor C.
Author_Institution
Sch. of EECS, Oregon State Univ., Corvallis, OR, USA
fYear
2010
fDate
May 30 2010-June 2 2010
Firstpage
1452
Lastpage
1455
Abstract
New architectures are proposed for the realization of micro-power analog-to-digital data converters. They are based on a time-interleaving and pipelining successive-approximation-register (SAR) structure. The resulting ADCs require very low power dissipation for medium-speed and medium-accuracy data conversion.
Keywords
analogue-digital conversion; energy-efficient time-interleaved SAR ADC; low power dissipation; medium-accuracy data conversion; medium-speed data conversion; micropower analog-to-digital data converters; pipelined SAR ADC; pipelining successive-approximation-register structure; time-interleaving successive-approximation-register structure; Analog-digital conversion; Biosensors; Capacitance; Capacitors; Clocks; Data conversion; Energy efficiency; Pipeline processing; Power dissipation; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location
Paris
Print_ISBN
978-1-4244-5308-5
Electronic_ISBN
978-1-4244-5309-2
Type
conf
DOI
10.1109/ISCAS.2010.5537328
Filename
5537328
Link To Document