Fully integrated PLL based clock generator for implantable biomedical applications

The design and verification of an ultra low power phase-locked loop (PLL) with application to implantable biomedical systems is presented. A systematic PLL design methodology is introduced, where the first step is a high level characterization of the system in MATLAB. The second step involves a transistor level implementation in Cadence using 0.35μm CMOS technology. The proposed low power and low area PLL consists of a phase-frequency detector, charge pump, second-order low pass filter, and a ring oscillator based voltage controlled oscillator (VCO). The final design is fully integrated and has a power consumption of approximately 492μW. The operating frequency of the PLL is 6.78MHz, which is the lowest frequency designated for the Industrial, Scientific, and Medical (ISM) band. The phase margin and the bandwidth of the PLL are, respectively, 61.9° and 2.96 Mhz.