• DocumentCode
    3378359
  • Title

    Equalization of interconnect propagation delay with negative group delay active circuits

  • Author

    Ravelo, Blaise ; Pérennec, André ; Roy, Marc Le

  • Author_Institution
    LEST - UMR CNRS 6165, Brest
  • fYear
    2007
  • fDate
    13-16 May 2007
  • Firstpage
    15
  • Lastpage
    18
  • Abstract
    In this paper, we propose a technique to compensate the propagation delay and losses in VLSI interconnects by using negative group delay (NGD) active circuits. This study uses the RLC models of interconnect lines currently considered in VLSI circuits. The circuit proposed here is based on a cell consisting of a Field Effect Transistor (FET) in parallel with a series RL passive network. We also describe the synthesis method to achieve simultaneousely a significant negative group delay and gain. Simulations allow us to first verify the performance of the NGD circuit and also show a restoration of the distorted signal shape as well as a reduction of propagation delay.
  • Keywords
    VLSI; active networks; integrated circuit interconnections; FET; RLC models; VLSI interconnects; interconnect lines; interconnect propagation delay; negative group delay active circuits; synthesis method; Active circuits; Circuit synthesis; FETs; Integrated circuit interconnections; Network synthesis; Passive networks; Propagation delay; Propagation losses; RLC circuits; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Signal Propagation on Interconnects, 2007. SPI 2007. IEEE Workshop on
  • Conference_Location
    Genova
  • Print_ISBN
    978-1-4244-1223-5
  • Electronic_ISBN
    978-1-4244-1224-2
  • Type

    conf

  • DOI
    10.1109/SPI.2007.4512196
  • Filename
    4512196