Evaluation of synthesis tools used in the design of a low-frequency ratemeter and a set-associative cache

This paper describes and evaluates the advantages and problems experienced during use of a logic synthesis tool for two projects carried out during an MSc course in “VLSI Systems Engineering” at UMIST. In addition, in the first project an implementation was first produced using schematics prepared conventionally, and comparison with the synthesised results is made. The synthesis tool used was “Autologic” from Mentor Graphics