Methodology of detection of spurious signals in VLSI circuits

Author

Moll, Francesc ; Rubio, Antonio

Author_Institution

Dept. of Electron. Eng., Univ. Politecnica de Catalunya, Barcelona, Spain

fYear

1993

fDate

19-22 Apr 1993

Firstpage

491

Lastpage

496

Abstract

The continuous reduction in scale achieved in microelectronic technology and the increasing switching speed may cause parasitic or spurious signals to appear, due to crosstalk. In this work, scale reduction of interconnections is analyzed, showing the increasing mutual capacitance and a model of crosstalk considering parasitic capacitive coupling is shown. A method for studying the propagation of crosstalk signals has been developed for combinational circuits. An algorithm for crosstalk faults test pattern generation is proposed taking into account the propagation limitation of the signals. Experimental results are shown

Keywords

VLSI; combinatorial circuits; crosstalk; fault location; integrated circuit testing; integrated logic circuits; logic testing; signal detection; MEDICI; VLSI circuits; capacitive coupling; combinational circuits; crosstalk; interconnections; mutual capacitance; parasitic signals; scale reduction; spurious signals; Circuit faults; Combinational circuits; Coupling circuits; Crosstalk; Integrated circuit interconnections; Microelectronics; Mutual coupling; Parasitic capacitance; Signal detection; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

European Test Conference, 1993. Proceedings of ETC 93., Third

Conference_Location

Rotterdam

Print_ISBN

0-8186-3360-3

Type

conf

DOI

10.1109/ETC.1993.246601

Filename

246601