DocumentCode
3380193
Title
Design of modified ESD protection structure with low-trigger and high-holding voltage in embedded high voltage CMOS process
Author
Lai, Tai-Hsiang ; Chen, Lu-An ; Tang, Tien-Hao ; Su, Kuan-Cheng
Author_Institution
ESD Eng. Dept., United Microelectron. Corp., Hsinchu, Taiwan
fYear
2011
fDate
10-14 April 2011
Abstract
In this work, we propose a modified structure with low trigger voltage and high holding voltage for efficient component-level and system-level ESD protections. Here, the TLP measurement, the TLU test and the technology computer-aided design (TCAD) simulation for the common and the modified HV N-channel MOSFETs are investigated in detail.
Keywords
CMOS integrated circuits; MOSFET; electrostatic discharge; HV N-channel MOSFET; TCAD simulation; TLP measurement; TLU test; embedded high voltage CMOS process; high-holding voltage; low-trigger voltage; modified ESD protection structure; technology computer-aided design; Current measurement; Electrostatic discharge; Implants; Junctions; Power supplies; Transient analysis; Voltage measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability Physics Symposium (IRPS), 2011 IEEE International
Conference_Location
Monterey, CA
ISSN
1541-7026
Print_ISBN
978-1-4244-9113-1
Electronic_ISBN
1541-7026
Type
conf
DOI
10.1109/IRPS.2011.5784505
Filename
5784505
Link To Document