Parallel sequence fault simulation for synchronous sequential circuits

Author

Kung, Chen-Pin ; Lin, Chen-Shang

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

1991

fDate

22-24 May 1991

Firstpage

419

Lastpage

423

Abstract

A parallel sequence fault simulation (PSF) algorithm for synchronous sequential circuits is presented. The algorithm divides a given test sequence into subsequences of equal length and then performs multiple-pass fault simulation with these subsequences in parallel. The experimental results on the benchmark circuits show that the speedup ratio over a differential serial fault simulator is 4.90 on average for random test sequences. Conceptually, the PSF is an extension of the parallel pattern single fault propagation (PPSFP) and it reduces to PPSFP for combinational circuits

Keywords

asynchronous sequential logic; automatic testing; fault location; logic testing; sequential circuits; PPSFP; benchmark circuits; combinational circuits; differential serial fault simulator; multiple-pass fault simulation; parallel pattern single fault propagation; parallel sequence fault simulation; random test sequences; speedup ratio; synchronous sequential circuits; test sequence; Benchmark testing; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Computational modeling; Logic; Partitioning algorithms; Performance evaluation; Sequential circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 1991. Proceedings of Technical Papers, 1991 International Symposium on

Conference_Location

Taipei

ISSN

1524-766X

Print_ISBN

0-7803-0036-X

Type

conf

DOI

10.1109/VTSA.1991.246753

Filename

246753