FPGA interconnect timing library based on the statistical method

This paper presents a statistical method to build up interconnect timing library of static timing analysis for FPGA design. To overcome a large number of negative values in the traditional interconnect timing library, the statistical method is introduced. The experimental results show that the proposed method could improve the positive ratio and achieve up to 22.35% on average. Compared to the tested delay results on the FPGA chip, the delay error rate can be reduced from 13.58% to 11%.