DocumentCode
3382444
Title
Design of a low-power low-phase-noise multi-mode divider with 25%-duty-cycle outputs in 0.13µm CMOS
Author
Hu, Song ; Li, Weinan ; Huang, Yumei ; Hong, Zhiliang
Author_Institution
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
fYear
2011
fDate
25-28 Oct. 2011
Firstpage
594
Lastpage
597
Abstract
A high-performance 25%-duty-cycle divider in 0.13μm CMOS for multi-mode wireless communication applications is presented. Compared with the conventional designs, this work features reduced power consumption and low phase noise by adopting the divide-by-2 divider with intrinsic 25%-duty-cycle outputs. The performance of this work has been demonstrated in a WCDMA/GSM multi-mode multi-band receiver implemented in 0.13μm CMOS.
Keywords
CMOS logic circuits; dividing circuits; integrated circuit design; low-power electronics; phase noise; CMOS; WCDMA/GSM; duty-cycle divider; low-power low-phase-noise multimode divider; multimode wireless communication; power consumption; size 0.13 mum; Analytical models; CMOS integrated circuits; Clocks; GSM; Multiaccess communication; Spread spectrum communication; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC (ASICON), 2011 IEEE 9th International Conference on
Conference_Location
Xiamen
ISSN
2162-7541
Print_ISBN
978-1-61284-192-2
Electronic_ISBN
2162-7541
Type
conf
DOI
10.1109/ASICON.2011.6157275
Filename
6157275
Link To Document