A 0.8ps minimum-resolution sub-exponent TDC for ADPLL in 0.13µm CMOS

This paper presents the design of a sub-exponent time-to-digital converter (TDC) that amplifies a time residue to improve both the time resolution and measurement range. The sub-exponent TDC quantizes the fractional time difference with a cascading chain of 2×time amplifiers. A digitally self-calibrated TA circuit is developed to achieve large input range and stable gain. Simulation results show that implemented in SMIC 0.13μm CMOS, the proposed TDC can achieve a minimum resolution of 0.8ps, a measurement range of 14bits, and a power dissipation of 2mW at 60MHz.