Improved lock-time in all-digital phase-locked loops due to binary search acquisition

A binary search algorithm for an improved settling time in phase-domain all-digital phase-locked loops (ADPLLs) is proposed. Therefore, an ADPLL structure for high-speed fractional-N frequency synthesis is adapted to extract the ratio between the reference and the output frequency in each reference cycle. A frequency detector compares the obtained ratio to the ideal value. The proposed control algorithm uses the frequency detector output to iteratively search for the desired tuning word. The binary search acquisition speeds-up the acquisition process significantly and suits digitally controlled oscillators with multiple varactor banks well. Behavioral simulations illustrate the proposed technique.