A digitally self-calibrated low-noise 7-bit folding A/D converter

In this paper, a low noise 65nm 1.2V 7-bit 1GSPS A/D converter with a digitally self-calibrated technique is proposed. The A/D converter is based on a folding-interpolation structure whose folding rate is 2 and its interpolation rate is 8. A digitally self-calibrated technique with a feedback loop and a recursive digital code inspection is described. The circuit reduces the variation of the offset voltage, due to process mismatches, parasitic resistors, and parasitic capacitances. The chip has been fabricated with a 65nm 1-poly 6-metal CMOS technology. The effective chip area is 0.87mm2 and the power consumption is about 110mW with a 1.2V power supply. The measured SNDR is drastically improved in comparison with the same ADC without any calibration.