High efficiency and low power multi-rate LDPC decoder design for CMMB

Author

Xiaobo, Jiang ; Hongyuan, Ii

Author_Institution

Sch. of Electron. & Iinformation Eng., South China Univ. of Technol., Guangzhou, China

fYear

2011

fDate

25-28 Oct. 2011

Firstpage

673

Lastpage

678

Abstract

High efficiency and low power LDPC decoder for CMMB that supports two rates has been designed in the paper. Layered min-sum algorithm and memory compression technology are adopted to reduce the usage of memory; backup memory method is applied to solve memory read/write conflict existing in CMMB LDPC code at a low cost of memory resource; operational unit multiplexing which can process 1/2 bit rate and 3/4 bit rate simultaneously is used so that the resource consumption of operational unit is reduced. The LDPC decoder designed in this paper is synthesized in the SMC0.18um process. The synthesized result has indicated that the area of designed CMMB LDPC decoder is 7.6mm2 and its power consumption is 132.8mW.

Keywords

low-power electronics; multiplexing; parity check codes; television broadcasting; CMMB LDPC decoder; China mobile multimedia broadcasting; SMC process; backup memory method; layered min-sum algorithm; low power LDPC decoder; memory compression technology; memory read/write conflict; memory resource; memory usage; multirate LDPC decoder; operational unit multiplexing; power 132.8 mW; power consumption; size 0.18 mum; Decoding; Field programmable gate arrays; Indexes; Parity check codes; Quantization; China mobile multimedia broadcasting (CMMB); FPGA; decoder; low density parity check (LDPC);

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC (ASICON), 2011 IEEE 9th International Conference on

Conference_Location

Xiamen

ISSN

2162-7541

Print_ISBN

978-1-61284-192-2

Electronic_ISBN

2162-7541

Type

conf

DOI

10.1109/ASICON.2011.6157295

Filename

6157295