Interconnect system compression analysis for multi-core architectures

One of the major problems associated with integrating multiple cores on a single chip is the performance demand it places on the interconnect system because of the combined traffic generated by multiple simultaneously executing threads. In this paper, we analyze interconnect compression potential in the two primary types of information - instructions and data - and important interconnect components in multi-core systems. In our study, lower compression ratio means better compression. We show great compression potential with 0.47-0.67 zero-information compression ratio, 0.28-0.29 zeroth-order compression ratio, and 0.11-0.14 first-order compression ratio obtained with different levels of compression specialization.