A single-event upset hardening technique for high speed MOS Current Mode Logic

In this paper, we introduce a SEU-hard MOS Current Mode Logic (MCML) sequential element that is used in high speed communication systems. We have implemented latches and flip-flops in 65 nm technology and show that the critical charge needed to upset the sensitive nodes in these circuits is increased with this proposed design. Simulation has been conducted for clock rates of 0.5, 1, 2 and 4 GHz. The results show the critical charge increases more than 5 times (>440%) with this design while the delay (32 ps) is acceptable for GHz operations.