A voltage feedback charge compensation technique for split DAC architecture in SAR ADCs

A voltage feedback charge compensation technique is presented to prevent the conversion nonlinearity due to the parasitic effect of split capacitive DAC structure in successive approximation register (SAR) ADCs. The charge compensation is achieved by using an open loop amplifier that performs voltage feedback to the DAC array via a compensation capacitor, which is easy to be implemented with very low power dissipation. The technique is utilized in the design of a 10b 80MS/s SAR ADC in 65-nm CMOS technology. The simulation results show that the proposed charge compensation technique can improve the Effective Number of Bits (ENOB) from 8.3bits to 9.6bits and differential/integral nonlinearity from 3LSB/1.65LSB to 0.45LSB/0.74LSB respectively with only 300 uW power dissipation in the proposed charge compensation circuitry.