• DocumentCode
    3383929
  • Title

    Efficient modulo 2n + 1 multi-operand adders

  • Author

    Vergos, H.T. ; Bakalis, D. ; Efstathiou, C.

  • Author_Institution
    Comput. Eng. & Inf. Dept., Univ. of Patras, Patras
  • fYear
    2008
  • fDate
    Aug. 31 2008-Sept. 3 2008
  • Firstpage
    694
  • Lastpage
    697
  • Abstract
    A new architecture for modulo 2n+1 multi-operand addition (MOMA) of weighted operands is introduced. It is based on the use of a translator circuit that enables to use n-bit operations for performing the weighted multi-operand addition. Our experimental results indicate that the proposed MOMAs offer significant savings in execution time compared to the previously proposed solutions that either require two parallel additions or a carry-save adder tree with twice the depth of the proposed while they can be implemented in less area in most cases.
  • Keywords
    adders; random number generation; carry-save adder tree; modulo 2n + 1 multi-operand adders; translator circuit; weighted multi-operand addition; Adders; Arithmetic; Circuits; Computer architecture; Convolution; Cryptography; Hardware; Informatics; Physics; Roundoff errors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics, Circuits and Systems, 2008. ICECS 2008. 15th IEEE International Conference on
  • Conference_Location
    St. Julien´s
  • Print_ISBN
    978-1-4244-2181-7
  • Electronic_ISBN
    978-1-4244-2182-4
  • Type

    conf

  • DOI
    10.1109/ICECS.2008.4674948
  • Filename
    4674948
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3383929