• DocumentCode
    3384684
  • Title

    High-performance architecture for Elliptic Curve Cryptography over binary field

  • Author

    Lai, Jyu-Yuan ; Hung, Tzu-Yu ; Yang, Kai-Hsiang ; Huang, Chih-Tsun

  • Author_Institution
    Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan
  • fYear
    2010
  • fDate
    May 30 2010-June 2 2010
  • Firstpage
    3933
  • Lastpage
    3936
  • Abstract
    This paper presents a high-performance Elliptic Curve Cryptography (ECC) architecture over binary field, based on the Montgomery scalar multiplication algorithm. The word-serial finite field arithmetic unit (AU) is proposed with the optimized operation scheduling and bit-parallel modular reduction. With a dedicated squarer, the 163-bit point scalar multiplication with coordinate conversion can be done in 20.9μs by the design of one AU, and can be further improved to 11.1μs by the one of three AUs, both using 0.13μm CMOS technology. The comparison with other ECC designs justifies the effectiveness of the proposed architecture in terms of performance and area-time efficiency.
  • Keywords
    computer architecture; public key cryptography; 163 bit point scalar multiplication; CMOS technology; Montgomery scalar multiplication algorithm; binary field; bit parallel modular reduction; elliptic curve cryptography; high performance architecture; operation scheduling optimization; word serial finite field arithmetic unit; Arithmetic; CMOS technology; Computer architecture; Computer science; Elliptic curve cryptography; Galois fields; Gold; Parallel architectures; Processor scheduling; Robustness;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
  • Conference_Location
    Paris
  • Print_ISBN
    978-1-4244-5308-5
  • Electronic_ISBN
    978-1-4244-5309-2
  • Type

    conf

  • DOI
    10.1109/ISCAS.2010.5537670
  • Filename
    5537670