Design of a link-controller architecture for multiple serial link protocols

This paper introduces a novel Multi-mode Serial Link Controller (MMSLC) for logic physical layer (PHY) and data link layer (DLL) of USB 3.0, PCIe 2.0 and SATA 3.0. Functions defined in these protocols are grouped based on qualifying similarities and workload. The framework consists of a configurable circuit, programmable accelerator and event processor for flexible implementation. This MMSLC can essentially substitute for three individual link-controllers across protocols, thus achieving area reduction. An RTL level implementation is fulfilled and the synthesis results are shown at the end of this paper.