DocumentCode
3385140
Title
Error control integration scheme for reliable NoC
Author
Yu, Qiaoyan ; Zhang, Bo ; Li, Yan ; Ampadu, Paul
Author_Institution
Dept. of Electr. & Comput. Eng., Univ. of Rochester, Rochester, NY, USA
fYear
2010
fDate
May 30 2010-June 2 2010
Firstpage
3893
Lastpage
3896
Abstract
To improve noise tolerance of link transmission and router buffers, we propose an error control scheme that integrates a powerful link error recovery method, an efficient buffer error correction coding, and an algorithm to further manage the loss of header and tail flits in a packet. With this method, header and tail flits can be effectively protected, reducing network saturation. Simulation results show the proposed scheme achieves up to a 9x improvement in operation time before saturation and 26% higher throughput than other error control methods. Simulations performed on a parallel FFT application mapped on a 4×4 mesh NoC demonstrate that the proposed error control scheme reduces the total computation time over a previous method in the high noise region.
Keywords
error correction codes; logic design; network-on-chip; NoC; buffer error correction coding; error control integration scheme; link error recovery method; link transmission; noise tolerance; parallel FFT; router buffer; Computational modeling; Concurrent computing; Energy management; Error correction; Error correction codes; Network-on-a-chip; Propagation losses; Protection; Tail; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location
Paris
Print_ISBN
978-1-4244-5308-5
Electronic_ISBN
978-1-4244-5309-2
Type
conf
DOI
10.1109/ISCAS.2010.5537694
Filename
5537694
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