Delay insensitivity verification of bit-level pipelined systolic arrays in dual-rail treshold logic

A delay-insensitivity analysis method is proposed for bit-level pipelined systolic arrays in dual-rail threshold logic style, where tradeoff between reliable delay insensitive operation and gate count is significant in determining overall circuit performance. The method targets at detecting input - dependent delay-insensitivity violations occurring due to early signal evaluation features, which are allowed for speed-up. The proposed method simplifies the verification task significantly so that analysis of a one-dimensional systolic array is reduced to analysis of three adjacent systoles for all possible eight early/late output evaluation scenarios. Delay-insensitivity violations are located and could be corrected at structural level, without diminishing the early output evaluation benefits. Since symbolic delays are used without imposing any timing assumptions on the environment; the proposed method is technology independent and robust against all physical and environmental variations.