DocumentCode
338606
Title
Partial scan using multi-hop state reachability analysis
Author
Sharma, Sameer ; Hsiao, Michael S.
Author_Institution
Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
fYear
1999
fDate
1999
Firstpage
121
Lastpage
126
Abstract
Sequential test generators fail to yield tests for some stuck-at-faults because they are unable to reach certain states necessary for exciting/propagating these target faults. Adding scan to the circuit increases reachability of these hard-to-reach and/or previously unreachable states. In this paper, we postulated that fewer scan flip-flops are needed to make these states reachable. The states necessary for detecting the hard-to-detect faults, when reached, will facilitate reaching other hard-to-reach states in one or more hops by the sequential test generator, resulting in significantly higher fault coverage. We collect information on the hard-to-reach, aborted, and easy states in our analysis. Results from our approach have indicated that higher fault coverage can be achieved with significantly fewer scan flip-flops for some circuits
Keywords
design for testability; fault diagnosis; flip-flops; logic testing; reachability analysis; sequential circuits; DFT; fault coverage; hard-to-detect faults; multi-hop state reachability analysis; partial scan; reachability; scan flip-flops; sequential test generators; stuck-at-faults; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Information analysis; Reachability analysis; Sequential analysis; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1999. Proceedings. 17th IEEE
Conference_Location
Dana Point, CA
ISSN
1093-0167
Print_ISBN
0-7695-0146-X
Type
conf
DOI
10.1109/VTEST.1999.766655
Filename
766655
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