Compact high gain CMOS op amp design using comparators

Author

Purcell, John ; Abdel-Aty-Zohdy, Hoda S.

Author_Institution

Dept. of Electr. & Syst. Eng., Oakland Univ., Rochester, MI, USA

Volume

2

fYear

1997

fDate

3-6 Aug. 1997

Firstpage

1050

Abstract

This paper discusses the design of a high gain, general purpose op amps. The op amp is based on a novel cascaded design using comparators and with structural simplicity approaching that of digital circuits. Ideally, the design tool presented here can be used to optimize gain and CMRR independent of the other op amp performance parameters. The designed op amp has 140 dB open-loop gain and 43 MHz unity gain frequency (GBW) in Berkeley Spice3f Level-2 simulation. The circuit is implemented using a 2.0 μm nwell CMOS process through MOSIS. The op amp is self-biased and requires only power supplies of ±2.5 V. It occupies an area of 113 μm×474 μm.

Keywords

CMOS analogue integrated circuits; SPICE; cascade networks; circuit analysis computing; comparators (circuits); digital simulation; operational amplifiers; -2.5 to 2.5 V; 140 dB; 2.0 micron; 43 MHz; Berkeley Spice3f Level-2 simulation; CMRR; MOSIS; cascaded design; comparators; high gain CMOS op amp; open-loop gain; power supplies; self-biased circuit; unity gain frequency; Bandwidth; Design methodology; Design optimization; Impedance; Laboratories; Microelectronics; Operational amplifiers; Performance gain; Systems engineering and theory; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on

Print_ISBN

0-7803-3694-1

Type

conf

DOI

10.1109/MWSCAS.1997.662257

Filename

662257