Delay fault testing of designs with embedded IP cores

Author

Kim, Hyungwon ; Hayes, John P.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA

fYear

1999

fDate

1999

Firstpage

160

Lastpage

167

Abstract

Conventional methods cannot effectively verify path delays of designs employing IP circuits (cores) whose implementation details are hidden. A delay fault ATPG method for such designs is proposed that employs a scan technique called selectively transparent scan (STS). Experimental results are presented which show that the STS method can robustly test paths of a specified delay range in core-based circuits, and substantially reduce test length

Keywords

VLSI; automatic test pattern generation; delays; integrated circuit testing; logic testing; ATPG method; STS method; core-based circuits; delay fault testing; embedded IP cores; intellectual property circuits; path delays; selectively transparent scan technique; test length reduction; Automatic test pattern generation; Circuit faults; Circuit testing; Delay effects; Design methodology; Intellectual property; Registers; Sociotechnical systems; System testing; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1999. Proceedings. 17th IEEE

Conference_Location

Dana Point, CA

ISSN

1093-0167

Print_ISBN

0-7695-0146-X

Type

conf

DOI

10.1109/VTEST.1999.766660

Filename

766660

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=338610