• DocumentCode
    338613
  • Title

    Efficient test generation for transient testing of analog circuits using partial numerical simulation

  • Author

    Variyam, Pramodchandran N. ; Hou, Junwei ; Chatterjee, Abhijit

  • Author_Institution
    Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
  • fYear
    1999
  • fDate
    1999
  • Firstpage
    214
  • Lastpage
    219
  • Abstract
    Dynamic transient tests can give better parametric and catastrophic fault coverage than both static DC and frequency domain AC tests in minimum test time. However determination of optimum transient tests is a complex search problem. Previous researchers have used accurate but computationally expensive fault simulation to guide the search for the optimum transient tests. In this paper we propose to use partial numerical simulation to guide the search for the optimum input test stimulus. The proposed method dynamically adjusts the number of Newton Raphson iterations and transient simulation time steps to perform fast test generation without sacrificing the test quality (fault coverage). This heuristic relies on the observation that although partial numerical circuit simulation may be inaccurate for determining the exact faulty circuit response to an applied test stimulus, it can determine very well how one test stimulus performs relative to another in detecting a fault. Simulation studies show that test generation using partial numerical simulation can generate high quality tests much faster compared to test generation methods based on accurate simulation without compromising test quality
  • Keywords
    Newton-Raphson method; analogue integrated circuits; automatic testing; integrated circuit testing; search problems; transient response; Newton Raphson iterations; analog ICs; complex search problem; dynamic transient tests; fault coverage; optimum transient tests; partial numerical simulation; test generation; test quality; transient simulation time steps; transient testing; Analog circuits; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Electrical fault detection; Frequency domain analysis; Numerical simulation; Performance evaluation; Search problems;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium, 1999. Proceedings. 17th IEEE
  • Conference_Location
    Dana Point, CA
  • ISSN
    1093-0167
  • Print_ISBN
    0-7695-0146-X
  • Type

    conf

  • DOI
    10.1109/VTEST.1999.766668
  • Filename
    766668