Track and hold circuit design and implementation in 65 nm CMOS technology for RF subsampling receivers

In this paper, two track and hold circuits are designed and implemented using 65 nm CMOS technology. The first circuit is based on a dummy switch topology to decrease the charge injection error. The second circuit uses a clock linearization technique to reduce the sampling instant inaccuracy. Simulation results show that the track and hold circuit based on dummy transistor technique presents the best performances in terms of rapidity and accuracy.