Design verification by concurrent simulation and automatic comparison

Verifying a synthesized hardware design is a tedious and time consuming task because the existing methods need designer´s efforts of checking the simulation results. We propose a new verification method which compares automatically the simulation results obtained for two designs: one before synthesis and one after synthesis. The two simulations, one for each design, run concurrently, comparing each pair of matching nets. The inconsistency is reported as soon as possible without necessarily completing the simulation run. Experimental results show that our method detects design errors earlier and easier than the existing methods.