Real-time implementation of an Automatic Voltage Stabilizer for HVDC Control

Classic HVDC systems are prone to voltage instability when operating on weak AC grids. This paper describes the implementation of a newly developed Automatic Voltage Stabilizer (AVS) in an existing CIGRÉ Benchmark Model for HVDC Controls and compares its performance with the Voltage Dependent Current Order Limitation (VDCOL) method. The tools used for the study are the eMegaSim OPAL-RT real-time simulator and the PSCAD/EMTDC digital simulator. With AVS, the power transfer can be optimized and kept at or close to the steady state stability limit thereby compensating for deficiencies of VDCOL. Using two different simulation environments provides important information on their capabilities to develop and improve future power system controls.