Reconfigurable multicore architecture for power flow calculation

This paper investigates the advantages of using multicore architectures, comprising high-performance processors and reconfigurable cores, for sparse Lower-Upper (LU) triangular decomposition, used in power flow calculations and contingency analysis. The proposed architecture combines a general-purpose processor with a custom row-reduction accelerator, sending streams of data to the accelerator through the use of a direct memory access module. The simple accelerator provides a speedup of 1.29X over existing high-performance sparse LU software on power system applications. As architectures with tightly-coupled processor cores and reconfigurable cores start to appear on the market, techniques presented in this paper provide a simple way to improve performance in important computations, such as those needed for power system analysis.