DocumentCode
3388271
Title
Synchronous equivalence for embedded systems: a tool for design exploration
Author
Hsieh, H. ; Sangiovanni-Vincentelli, A. ; Balarin, F. ; Lavagno, L.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fYear
1999
fDate
7-11 Nov. 1999
Firstpage
505
Lastpage
509
Abstract
Design exploration consists of analyzing several alternative implementations of the "same" function to determine the most desirable one. A fundamental question is whether an "implementation" is consistent with the high-level specification or whether two implementations are "equivalent". We define synchronous equivalence for embedded systems that strongly resembles the concept of functional equivalence for sequential circuits. We then present equivalence analysis algorithms that are of low polynomial complexity. We show an example of application of the algorithms to a real-life design (a shock absorber controller) and demonstrate that synchronous equivalence opens up design exploration avenues uncharted before.
Keywords
circuit CAD; computational complexity; embedded systems; finite state machines; shock control; design exploration tool; embedded systems; equivalence analysis algorithms; functional equivalence; high-level specification; polynomial complexity; real-life design; sequential circuits; shock absorber controller; synchronous equivalence; Algorithm design and analysis; Clocks; Computational modeling; Design methodology; Embedded system; Latches; Power system modeling; Sequential circuits; Space exploration; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1999. Digest of Technical Papers. 1999 IEEE/ACM International Conference on
Conference_Location
San Jose, CA, USA
ISSN
1092-3152
Print_ISBN
0-7803-5832-5
Type
conf
DOI
10.1109/ICCAD.1999.810702
Filename
810702
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