DocumentCode
3388434
Title
P-channel Tunneling Field Effect Transistor (TFET): Sub-10nm technology enablement by GaSb-InAs with doped source underlap
Author
Sharma, Ankit ; Goud, A. Arun ; Roy, Kaushik
Author_Institution
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
fYear
2015
fDate
21-24 June 2015
Firstpage
151
Lastpage
152
Abstract
Summary form only given. This work proposes sub-10nm p-TFET showing sub-60 mv/dec SS for several orders of current. An 8-T SRAM cell evaluation indicates that TFETs can perform like FinFETs near-threshold voltages while consuming 100x lower standby power.
Keywords
III-V semiconductors; MOSFET; SRAM chips; field effect transistors; gallium compounds; indium compounds; low-power electronics; tunnel transistors; FinFET; GaSb-InAs; SRAM cell evaluation; doped source underlap; near-threshold voltages; p-TFET; p-channel tunneling field effect transistor; Arrays; Logic gates; Random access memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Device Research Conference (DRC), 2015 73rd Annual
Conference_Location
Columbus, OH
Print_ISBN
978-1-4673-8134-5
Type
conf
DOI
10.1109/DRC.2015.7175600
Filename
7175600
Link To Document