• DocumentCode
    3388460
  • Title

    A background KDCO compensation technique for constant bandwidth in all-digital phase-locked loop

  • Author

    Lee, Sung-Pah ; Cho, SeongHwan

  • Author_Institution
    Dept. of EECS, KAIST, Daejeon, South Korea
  • fYear
    2010
  • fDate
    May 30 2010-June 2 2010
  • Firstpage
    3401
  • Lastpage
    3404
  • Abstract
    This paper presents an ADPLL using a background KDCO compensation technique to achieve PVT tolerant loop bandwidth and damping factor over a broad tuning range using a linear averaging estimation of KDCO. Simulation results show that the proposed ADPLL achieves output frequency range from 1GHz to 4.5GHz and the reference frequency range from 10MHz to 80MHz with a constant damping factor and the bandwidth to the reference frequency ratio determined by the digital loop filter.
  • Keywords
    digital filters; digital phase locked loops; PVT tolerant loop; all-digital phase-locked loop; background KDCO compensation technique; digital loop filter; frequency 1 GHz to 4.5 GHz; frequency 10 MHz to 80 MHz; linear averaging estimation; Bandwidth; Calibration; Damping; Digital filters; Digital integrated circuits; Frequency; Jitter; Phase estimation; Phase locked loops; Tuning;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
  • Conference_Location
    Paris
  • Print_ISBN
    978-1-4244-5308-5
  • Electronic_ISBN
    978-1-4244-5309-2
  • Type

    conf

  • DOI
    10.1109/ISCAS.2010.5537860
  • Filename
    5537860
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3388460