Double-via insertion enhanced X-architecture clock routing for reliability

As the VLSI technology node advances into the nanometer era, reducing the yield loss induced by via failures is one of the critical problems in design for manufacturability (DFM). Double-via insertion (DVI) in the post-routing stage is a highly recommended method by foundries for improving yield and reliability. This work applies the DVI method in the post stage of an X-architecture clock routing to improve via yield. The proposed DVI-X algorithm constructs the bipartite graphs of the partitioned clock routing layout with single vias and redundant-via candidates (RVCs). Then, a set of maximum cliques is obtained from the bipartite graph for solving the DVI problem. Experimental results on benchmarks indicate that DVI-X can achieve higher double-via insertion rate by 2.925% than other works.