A generalized HSPICE macro-model for spin-valve GMR memory bits

This work presents the first generalized circuit macro-model for a Giant-Magneto-Resistance (GMR) memory bit. It is applicable for spin-valve structures and can be easily extended to pseudo-spin-valve structures. The macro-model is realized as a four terminal sub-circuit which emulates GMR bit behavior over a wide range of sense and word line currents. The non-volatile and nonlinear nature of GMR memory bits are accurately represented by this model and simulations of non-volatile GMR latch structures with HSPICE show expected outcomes. The model is flexible and relatively simple: ranges of the write/read currents and bit resistance values are incorporated as parameterized variables and no semiconductor devices are used within the model.