• DocumentCode
    3390039
  • Title

    1 mu m CMOS gate array radiation hardened technology

  • Author

    Owens, Alexander H. ; Yee, Abraham ; Toutounchi, Shahin ; Lyu, Michael ; Schneider, William C. ; Dantas, Armando R V

  • Author_Institution
    LSI Logic Corp., Santa Clara, CA, USA
  • fYear
    1992
  • fDate
    1992
  • Firstpage
    67
  • Lastpage
    71
  • Abstract
    A 1 mu m radiation hardened ASIC gate array HCMOS technology is introduced which has a total dose specification of 3 Mrads(Si). This is based on both X-ray and Co60 gamma ray radiation test results at both the device and circuit level. Transistor threshold shifts of less than 0.45 volts are observed for both N and P channel devices in both on and off bias configurations up to a total dose of 5 Mrad. Also presented are circuit data including RAMs, and ring oscillator data illustrating the radiation tolerance of this technology. The circuit was functional with little additional degradation up to the maximum total dose level tested of 15 Mrad (Si). Single event cross section data gives a threshold LET on this technology of 52 MeV-cm2/mg using 254 MeV Ni and 320 MeV Au. Dose rate data on this technology gives an upset threshold level greater than 1E9 rads (Si)/sec. No SEE latch-up is observed for LET values measured up to 200 MeV-cm2/mg.
  • Keywords
    CMOS integrated circuits; VLSI; X-ray effects; aerospace instrumentation; aerospace simulation; application specific integrated circuits; gamma-ray effects; integrated circuit testing; logic arrays; logic testing; military equipment; radiation hardening (electronics); 1 micron; 3 Mrad; 5 Mrad; ASIC gate array; CMOS gate array; HCMOS; RAMs; SEU cross section data; VLSI; X-ray radiation test; dose rate effects; gamma ray radiation test; military applications; radiation hardened technology; radiation tolerance; ring oscillator data; spaceborne electronics; threshold LET; transistor threshold shifts; upset threshold level; Application specific integrated circuits; CMOS logic circuits; CMOS technology; Circuit testing; Large scale integration; Logic arrays; Packaging; Radiation hardening; Space technology; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Radiation Effects Data Workshop, 1992. Workshop Record., 1992 IEEE
  • Conference_Location
    New Orleans, LA, USA
  • Print_ISBN
    0-7803-0930-8
  • Type

    conf

  • DOI
    10.1109/REDW.1992.247322
  • Filename
    247322