The enhancement of MOSFET electric performance through strain engineering by refilled sige as Source and Drain

Mismatched lattice constants between SiGe and silicon can cause the strain making the mobility improved. SiGe are grown underneath the channel apparently to form global strain over the whole devices, while Source/Drain refilled with SiGe would squeeze or pull up the devices uni-axially. The I_D-V_G characteristics curves and the maximum trans-conductance (g_m) using strain engineering are observed to be superior to the baseline. Nevertheless, the breakdown voltages with strain engineering no longer enjoy as robustly as ones without.