Estimates of integrated circuit yield components from in-line inspection data and post-process sort data

Increasing process complexity and shortening cycle times identification of defect traditional techniques such as post processing delayering are useful, such methodologies are somewhat tedious and not very amenable to statistical manipulation. A comprehensive yield management approach must utilize several pieces of information commonly available in fabs today such as end-of-process wafer sort data and in-process defect data from automated defect inspection equipment. With the help of such data the magnitude of yield loss accounted for by specific inspection steps and the relative culpability of the observed defects in causing faults are estimated. Aspects of the overlay coincidence methodology described here include partial die area inspected and multiple defects per die not covered elsewhere