A 25 Gbps inductorless receiver front-end in 65-nm CMOS for serial links

This paper presents a 25Gbps inductorless receiver front-end in a standard 65nm CMOS technology. The receiver front-end consists of a variable gain amplifier as the first stage and a variable peaking amplifier as the second stage. The first-stage amplifier uses a regulated cascode (RGC) amplifier to achieve high gain and a split current technique to adjust gain. The second stage amplifier uses dual-loop active feedback to adjust peaking without altering the DC gain. The fabricated circuit achieves differential gain of 20dB and a bandwidth of 23GHz. The circuit occupies an area of 50×56μm², which is less than one-tenth of that for previously reported receivers and limiting amplifiers exceeding 20Gbps.