Parallel CRC Logic Optimization Algorithm for High Speed Communication Systems

Author

Yi, Hyunbean ; Song, Jaehoon ; Park, Sungju ; Park, Changwon

Author_Institution

Dept. of Comput. Sci. & Eng., Hanyang Univ., Seoul

fYear

2006

fDate

Oct. 2006

Firstpage

1

Lastpage

5

Abstract

This paper presents a new optimization algorithm for designing parallel cyclic redundancy check (CRC) circuits widely adopted to detect burst errors in high-speed communications. Our heuristic algorithm is focused on minimizing the logic level and finding XOR terms shared as many as possible. An Ethernet 32-bit CRC generator, which was designed and mapped to FPGA and a standard cell library, shows the superiority of our approach in reducing the delay and area overhead

Keywords

cyclic redundancy check codes; field programmable gate arrays; local area networks; Ethernet; FPGA; burst error detection; cyclic redundancy check circuit; field programmable gate array; heuristic algorithm; high speed communication system; parallel CRC logic optimization algorithm; standard cell library; Algorithm design and analysis; Circuits; Cyclic redundancy check; Delay; Design optimization; Ethernet networks; Field programmable gate arrays; Heuristic algorithms; Libraries; Logic;

fLanguage

English

Publisher

ieee

Conference_Titel

Communication systems, 2006. ICCS 2006. 10th IEEE Singapore International Conference on

Conference_Location

Singapore

Print_ISBN

1-4244-0411-8

Electronic_ISBN

1-4244-0411-8

Type

conf

DOI

10.1109/ICCS.2006.301450

Filename

4085745