Design and realization of reed-solomon codec based on FPGA technique

Author

Jiabin You ; Shaochuan Wu

Author_Institution

Commun. Res. Center, Harbin Inst. of Technol., Harbin, China

fYear

2011

fDate

19-22 Aug. 2011

Firstpage

2086

Lastpage

2089

Abstract

In this paper, we present a design and realization of RS(255, 223) codec targeted for an image transmission system. The low-complexity pipelined RS(255, 223) decoder with the Berlekamp-Massey (BM) linear feedback shift register (LFSR) algorithm used is able to operate at a clock frequency of 120MHz and has a data throughout rate of 960 Mb/s. Simulations displayed by Signal Tap II software which derives the actual signals run inside the Cyclone II FPGA manufactured by Altera certificate the analysis of each part of the codec. Also, the BER performance of RS(255, 223) simulated by Matlab is shown at the end of the paper.

Keywords

Reed-Muller codes; codecs; field programmable gate arrays; image coding; Berlekamp-Massey linear feedback shift register algorithm; Cyclone II FPGA; FPGA technique; LFSR algorithm; RS 223 decoder; RS 255 decoder; Reed-Solomon codec; Signal Tap II software; bit rate 960 Mbit/s; image transmission system; pipelined decoder; Algorithm design and analysis; Codecs; Computer architecture; Decoding; Polynomials; Reed-Solomon codes; Registers; RS codec; RS decoder; Simulation;

fLanguage

English

Publisher

ieee

Conference_Titel

Mechatronic Science, Electric Engineering and Computer (MEC), 2011 International Conference on

Conference_Location

Jilin

Print_ISBN

978-1-61284-719-1

Type

conf

DOI

10.1109/MEC.2011.6025902

Filename

6025902