The design of FPGA´s high speed configurable logic units

This paper presents the research and design of FPGA´s high speed configurable logic units under very deep sub-micron (VDSM) technology. The keystone is the design of FPGA´s two basic elements - look-up table (LUT) and configurable register. Decoding circuit and CMOS transmission gate (TG) is applied to build LUT to solve the problems brought by the VDSM technology, such as the low power supply voltage and comparatively high threshold voltage loss. CMOS TG and designed control circuit is used to implement the complex function of FPGA´s configurable register to reduce the critical path´s delay. Experimental result shows the achieved speed is comparable and even faster than Xilinx´s Virtex4, while retaining small leakage power and area.