Mapping regular algorithms onto multilayered 3-D reconfigurable processor array

Extends the systolic array approach and presents a 3D reconfigurable array processor with a method for mapping algorithms onto this processor. The 3D multilayered array consists of 3D layers, which are connected with each other only by edges. New methods for reducing the latency time and increasing the throughput rate in comparison to classical systolic arrays are introduced. The classical space-time mapping of a problem onto systolic arrays is extended by the following techniques: (1) the dimensionality of a problem is increased by partitioning the range of indices, (2) the piecewise regular pipe-structures are used for spreading shared data and for gathering the partial results of a reduction operator. The paper illustrates this method using 3D convolution of two sequences of sizes n and N. A multilayered 3D array with area complexity O(sn) (O/spl les/s\n\n\t\t