DocumentCode
3398935
Title
A fast-lock PLL with over-tuning control
Author
Chao He ; Kwasniewski, T.
Author_Institution
Dept. of Electron., Carleton Univ., Ottawa, ON, Canada
fYear
2012
fDate
Oct. 29 2012-Nov. 1 2012
Firstpage
1
Lastpage
3
Abstract
The lock-in speed is an important performance criterion for ranking a frequency synthesizer, especially in wireless applications where the acquisition speed of the synthesizer determines how fast the communication can be switched from one channel to another or from off state to on. A novel fractional-N Phase Locked Loop (PLL) featuring fast acquisition and wide tuning range is proposed in this paper. The proposed method was verified in Simulink simulation.
Keywords
frequency synthesizers; phase locked loops; tuning; Simulink simulation; acquisition speed; fast-lock PLL; fractional-N phase locked loop; frequency synthesizer; lock-in speed; over-tuning control; performance criterion; wireless applications; Bandwidth; Clocks; Phase locked loops; Tuning; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
Conference_Location
Xi´an
Print_ISBN
978-1-4673-2474-8
Type
conf
DOI
10.1109/ICSICT.2012.6466718
Filename
6466718
Link To Document