A systolic exponentiator for finite fields GF(2m)

The author presents a novel parallel-in-parallel-out bit-level systolic array with unidirectional data flow for computing exponentiation in GF(2^m). The array is highly regular and modular, and thus well it is suited to VLSI implementation. In addition, it can provide the maximum throughput in the sense of producing new results at a rate of one per clock cycle. Compared to a previously known systolic (GF2^m) exponentiator with the same throughput performance, the proposed system requires much less chip area, has smaller latency, and makes it easier to incorporate fault-tolerant design