Error correction circuit using difference-set cyclic code

Author

Kato, Yukihiro ; Morita, Tomokazu

Author_Institution

Graduate Sch. of Eng., Tokyo Metropolitan Inst. of Technol., Japan

fYear

2003

fDate

21-24 Jan. 2003

Firstpage

585

Lastpage

586

Abstract

An error correction receiver using a difference-set cyclic code has been designed. Highly reliable operation, short critical path, and small circuit size are key issues. The synchronization circuit is optimized in its circuit size by detecting 10 kinds of bit sequences for synchronization. The circuit action is governed by a state machine combined with a Johnson counter and a timer. The critical path length is estimated to be 4.8, which is less than the average value.

Keywords

binary sequences; circuit optimisation; counting circuits; cyclic codes; error correction; error correction codes; finite state machines; logic design; shift registers; synchronisation; timing circuits; Johnson counter; LFSR; bit sequence detection; circuit optimization; circuit size reduction; critical path length; difference-set cyclic code; error correction receiver; linear feedback shift register; operation reliability; state machine; synchronization circuit; timer; Adders; Counting circuits; Data engineering; Design engineering; Error correction codes; Logic circuits; Reliability engineering; Shift registers; Synchronization; Systems engineering and theory;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific

Print_ISBN

0-7803-7659-5

Type

conf

DOI

10.1109/ASPDAC.2003.1195090

Filename

1195090