A deep submicron power estimation methodology adaptable to variations between power characterization and estimation

Author

Eckerbert, Daniel ; Larsson-Edefors, Per

Author_Institution

Chalmers Univ. of Technol., Goteborg, Sweden

fYear

2003

fDate

21-24 Jan. 2003

Firstpage

716

Lastpage

719

Abstract

Traditionally, RTL power estimation techniques characterize a component for a fixed environment (most importantly load capacitance, activity, and operating frequency). This article presents a solution to problems originating from the ineluctably changing operating conditions such as differing load capacitance due to different applications; different activity and operating frequency. These techniques can be used in design power reduction.

Keywords

circuit simulation; integrated circuit design; integrated circuit modelling; logic design; logic simulation; RTL power estimation; circuit activity level; component characterization; load capacitance; operating condition variations; operating environment; operating frequency; power characterization variations; power estimation methodology; power reduction techniques; Capacitance; Costs; Differential equations; Digital systems; Energy consumption; Frequency estimation; Gate leakage; Power system interconnection; Subthreshold current; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific

Print_ISBN

0-7803-7659-5

Type

conf

DOI

10.1109/ASPDAC.2003.1195114

Filename

1195114