DocumentCode
3401073
Title
Performance optimization of synchronous control units for datapaths with variable delay arithmetic units
Author
Kim, Euiseok ; Lee, Dong-Ik ; Saito, Hiroshi ; Nakamura, Hiroshi ; Lee, Jeong-Gun ; Nanya, Takashi
Author_Institution
RCAST, Univ. of Tokyo, Japan
fYear
2003
fDate
21-24 Jan. 2003
Firstpage
816
Lastpage
819
Abstract
Nowadays, variable delay arithmetic units have been used for implementing a datapath of a target system in pursuit of performance improvement. However, the adoption of variable delay arithmetic units requires modification of a typical synchronous control unit design methodology. A telescopic arithmetic unit based methodology is one of the representative methodologies used to design synchronous control units for variable delay datapaths. In this paper, we propose two optimization methods for it. The proposed optimization techniques are analyzed in order to show their performance improvement effects explicitly.
Keywords
circuit optimisation; digital arithmetic; finite state machines; logic design; TAU; VDAU; datapath synchronous control unit; finite state machine; performance optimization; synchronous control unit; telescopic arithmetic unit; variable delay arithmetic unit; variable delay datapaths; Arithmetic; Automatic control; Clocks; Control systems; Delay effects; Design methodology; Optical design; Optimization methods; Performance analysis; Signal generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific
Print_ISBN
0-7803-7659-5
Type
conf
DOI
10.1109/ASPDAC.2003.1195130
Filename
1195130
Link To Document